1. Field of the Invention
The present invention relates in general to a display memory and an address generator for addressing the display memory and in particular to an array-word-organized display memory and an address generator with a time-multiplexed address bus for addressing word-aligned and non-word-aligned arrays of pixels in the display memory.
2. Description of Prior Art
Images are displayed on a display screen by scanning pixels in a display memory. To avoid flicker, updating a frame of pixels should be done in less than a typical frame time, e.g. 1/60 of a second. Hence, for a screen with 1K.times.1K pixels, the bandwidth required is approximately 60 megapixels/second.
In order to satisfy the above-described required bandwidth, it has been the practice to organize display memories by words wherein each word comprises a plurality of pixels.
Heretofore, one such type of display memory has comprised a plurality of words which are aligned along a scan line so that the video refresh controller could simply load each word in a shift register and shift them out as video data for the screen. On the other hand, in order to change the image appearing on the screen, a word of data was accessed and one or more pixels in the word were changed, each such access comprising a read and a write, requiring a minimum of two memory cycles.
A disadvantage of the above-described horizontally word-aligned organization was that, if the pixels to be updated crossed word boundaries, not only in a horizontal direction but also in a vertical direction, as in the case of vectors and characters, an unnecessarily high number of memory cycles were required to complete an update. For example, to load an 8.times.10 character that spans two words could take as many as 20 memory cycles instead of the 10 cycles required in the aligned case.
To at least partially overcome the disadvantages of horizontally word-aligned display memory organizations, word-array memory organizations have been proposed.
In an article entitled, A VSLI Architecture for Updating Raster-Scan Displays by S. Gupta and R. F. Sproull, Computer Graphics, Vol. 15, Number 3, August 1981, pp. 71-78, the authors disclose a display memory in which the pixels are organized in 8.times.8 arrays with each array comprising 64 pixels. In this organization, it is stated that an 8.times.10 character can be transferred in maximum 4 memory cycles.
In the apparatus proposed by Gupta et al, a plurality of 64 16-kilobit memory chips with each chip providing one of the pixels in an 8.times.8 array, a plurality of 8 address buses, each bus comprising 7 address lines, 8 RAS lines, 8 CAS lines and a graphics processor having two address outputs, are provided. The 64 chips may be considered as being arranged in 8 rows and 8 columns. One of the 8 address buses and one of the CAS lines is routed through each of the 8 columns of memory chips. One of the 8 RAS lines is routed through each of the 8 rows of memory chips. The 8 address buses are coupled to a pair of address outputs of the graphics processor. The CAS lines are coupled in parallel to a CAS strobe output of the graphics processor. The RAS lines are coupled to separate RAS strobe outputs of the graphics processor.
Assuming that the pixels in an arbitrary 8.times.8 pixel array fall within the boundaries of four 8.times.8 word-aligned arrays, that the address of the upper leftmost word-aligned array is X,Y, that the address of the array to the right of X,Y is X+1,Y, that the address of the array below X,Y is X,Y+1, and that the address of the pixels in the array to the right of X,Y+1 is X+1,Y+1, then the address of a pixel in the X,Y array is x*8+i,Y*8+j, where i is the number of pixels from the left edge of the word-aligned array X,Y and j is the number of pixels below the top edge of the word-aligned array X,Y.
To address the arbitrary array, wherein the upper leftmost pixel is located at (X*8+i,Y*8+j), takes three time periods. In the first time period, t.sub.1, the address Y is placed on all of the 8 address buses and the RAS lines on the (8-j) rows from the bottom of the display memory array are strobed. In the second time period, t.sub.2, the address Y+1 is placed on all of the 8 address buses and the RAS lines on the j rows from the top of the display memory are strobed. At this point, all of the chips have the correct Y address. In the third time period, the address X+1 is placed on the first (8-i) address buses of the display memory, the address X is placed on the rest of the i address buses of the display memory and the CAS lines to all of the memory chips are strobed. At this point, all of the chips have the correct X and X+1 addresses and the pixel data for the selected 8.times.8 unaligned-word-array is available.
While the above-described prior known array-word addressing scheme is advantageous in that it allows for addressing an arbitrary 8.times.8 word-array in three time periods, it also has a number of disadvantages. For example, the large number of conductors required between the graphics processor and the memory chips, e.g. 8 buses of 7 wires each for an 8.times.8 array of 16 kilobit chips, all of which carry identical information in the first and second memory cycles, is very difficult to fabricate because the conductors are so narrow and closely spaced. Moreover, as the size of the chips is increased the number of such conductors must also be increased, making the fabrication of the memory system even more difficult. For example, a 64 kilobit chip requires 8 address lines, a 256 kilobit chip requires 9 address lines, etc. Additionally, the graphics processor requires a special port dedicated to outputting the X+1 address at the same time as the X address, the scheme disallows partial X access to the 8.times.8 array thereby disallowing banking in the X direction, the size of the elementary array can't be changed dynamically from the original 8.times.8 array and the scheme disallows interleaved banking. The term "banking" as used here is a term defining the use of two distinct groups of 64 memory chips. "Interleaving" is a scheme that allows alternating arrays to belong to alternate banks. For example: array X,Y belongs to bank 0, array X+1,Y belongs to bank 1, array X+2Y belongs to bank 0, array X+3,Y belongs to bank 1, etc.